1. Field of the Invention
The present invention generally relates to circuit board structures and fabrication methods of the same, and more specifically, to a circuit board structure with fine circuits and a fabrication method of the same.
2. Description of Related Art
Owing to the evolution of semiconductor package technology, different package models of semiconductor devices have been developed. A traditional method for fabricating semiconductor devices comprises the following steps: mounting a semiconductor element, e.g. an integrated circuit, on a package substrate or a leadframe; electrically connecting the semiconductor element to the package substrate or the leadframe and performing encapsulation with an encapsulant; wherein ball grid arrays (BGAs), such as PBGA, EBGA, FCBGA, and others, are advanced semiconductor package technologies applied. The features of these technologies are: mounting a semiconductor element on one side of a packaging substrate; implanting a plurality of solder balls on the other side of the packaging substrate in a grid array pattern, thus allowing a carrier board of the semiconductor element to be capable of accommodating more input/output connections within the same unit area and thereby meeting demands for high integration of semiconductor chips, wherein the semiconductor element can be entirely soldered and electrically connected to external electronic devices via the solder balls.
To meet operational requirements for high-performance chips, such as microprocessors, chip sets, and graphic chips, it is necessary to enhance the functions of wired circuit boards regarding, for example, chip signal transmission, bandwidth, and impedance control, in order to accordingly answer to the trends of high I/O number packages. However, to fit in with the developing trend of semiconductor package towards light weight, small size, multiple functions, high speed, and high frequency, circuit boards for packaging semiconductor chips have been trending towards fine lines and small apertures; size of a circuit lines of the present circuit board, including line width, pitches between lines, aspect ratio, and etc., has been reduced from traditional 100 μm to 30 μm, and the developing trend is continuously towards smaller lines with great precision.
In order to enhance wiring layout precision of a circuit boards applied in semiconductor chip packages, semiconductor industry has developed build-up technology, namely a plurality of dielectric layers as well as circuit layers are alternately laid on a core circuit board by means of a circuit layers build-up technology, and then a plurality of conductive vias are formed in the dielectric layers for providing electrical connections among the circuit layers; in addition, a solder mask is formed on top of the topmost circuit layer to protect circuit layers thereunder, and the solder mask has a plurality of openings for exposing electrically connecting pads on the topmost circuit layer.
Please refer to FIGS. 1A through 1C, which are cross-sectional views of a fabrication method of a known circuit board with multiple circuit layers; first, as shown in FIG. 1A, provide a carrier board 10, which is a circuit board thereon a circuit layer 11 has already be fabricated, and the circuit layer 11 has at least one electrically connecting pad 110; an then, as shown in FIG. 1B, form a solder mask 12 on surfaces of the circuit layer 11 and the carrier board 10, a general thickness thereof is 21 μm; at last, as shown in FIG. 1C, have the solder mask 12 go through a patterning process of exposing, developing, etching, etc., thus a plurality of openings 120 are formed in the solder mask 12 to expose the electrically connecting pads 110 of the circuit layer 11.
However, in the aforementioned fabrication process of solder mask on the surface of the circuit board with multiple circuit layers, the solder mask 12 is made of impure material that has impurities, such as macroparticles of about 10 μm in diameter, therefore when the solder mask 12 is formed on the surface of the carrier board 10 that has circuit layer 11, fluidity and filling property of the solder mask 12 are greatly affected by the impurities thereof, and consequently the solder mask 12 cannot completely permeate through gaps within the circuit layer 11 between lines, between line and electrically connecting pad, as well as between electrically connecting pads. The gaps must be widened in order to be filled with the solder mask. Therefore, the pitches between lines must be enlarged in a wiring process, and then area on the circuit board available for wiring is consequently reduced. The outcome is definitely a disadvantageous situation for fabricating circuit of fine lines.
Besides, the solder mask 12 with macroparticles has relatively poor insulation and a relatively high dielectric constant, thus migration of metal atoms of the circuit layer 11 in the solder mask 12 is likely to happen, and consequently impedance between lines will not fit in with product specification, and then electric signal interference between lines happens; in a worse scenario of migration of metal atoms, the solder mask 12 will produce metal hyphae, in such situation, when the circuit layer 11 is electrified, terminals of the metal hyphae tend to discharge electricity, consequently electricity quality and capability of the circuit are greatly diminished; it is obviously that the pitches between lines should be spacious enough to prevent migration of metal atoms from happening, therefore the demand for applying fine circuit lines cannot be reached.
In view of the above, it is a highly urgent issue in the industry for how to provide a circuit board structure and a fabrication method of the same, which can effectively prevent metal atoms from migrating in the solder mask as well as prevent metal hyphae from discharging electricity caused by poor fluidity and filling property of the solder mask due to macroparticles thereof as happened in prior art, and can avoid disadvantage of being unfit to fabricate circuit boards with fine circuit lines.